1. Field of the Invention
The present invention relates to a vacuum deposition process for forming electronic elements on a substrate and, more particularly, to a method of planarizing the contact region of a via in a continuous inline vacuum deposition process.
2. Description of Related Art
In a multi-layer electronic device, such as a semiconductor device, a via is needed to provide a conductive path through a non-conductive layer (insulator or dielectric layer) in order to connect two or more conducting layers. A via is a structure formed by filling or lining a via hole (or through-hole) with conductive material which is used to electrically connect two or more conducting layers in a substrate.
The creation of vias in a typical microcircuit fabrication process is accomplished by applying a pattern or stencil of etch-resistant material over the layer through which the via is to be formed and subsequently applying an etching medium to the wafer to remove areas unprotected by the etch-resistant material. The etch-resistant material, known as photoresist, is patterned by a process called photolithography, which is a subtractive wet chemical process. Because photolithography is a subtractive process, it lends well to the formation of via holes in the manufacture of multi-layer electrical devices. The multi-layer electrical device fabrication process includes numerous deposition and etching steps in order to define appropriate patterns of conductors, insulators and vias. Exemplary photolithography processing steps that produce vias in a multi-layer electrical device include: applying a photoresist on an insulator layer; exposing the photoresist to a suitable wavelength of light to define the via locations therein; developing the photoresist whereupon photoresist is left everywhere except at the via locations; baking the photoresist; etching the insulator layer by way of the via holes in the photoresist, whereby the etchant material attacks the insulator layer but not the photoresist or the conductor below; and stripping off the remaining photoresist, thereby leaving the insulator layer with via holes therethrough on top of the conductive layer. As can be seen, the multi-layer electrical device fabrication process includes numerous deposition and etching steps in order to define vias.
Because of the number of steps required to form a multi-layer electronic device utilizing the photolithography manufacturing process, foundries of adequate capacity for volume production are expensive. Furthermore, because of the nature of the fabrication process, the production equipment must be utilized in a class one or class ten clean room. In addition, because of the amount of equipment needed and the size of each piece of equipment, the clean room must be relatively large.
Alternatively, a vapor deposition shadow mask process is well known and has been used in microelectronics manufacturing. The vapor deposition shadow mask process is a significantly less costly and less complex manufacturing process than the photolithography manufacturing process. However, in contrast to the photolithography manufacturing process, the vapor deposition shadow mask process is an additive process that is performed in a vacuum environment.
A problem associated with forming a via by the vapor deposition shadow mask process is that, in order to deposit a conductor layer atop an insulator layer and through a via hole whereby the conductor layer makes contact with another conductor layer, there is a limit to the ratio of via hole depth to conductor layer thickness for ensuring that no discontinuity of conductor material occurs as it is deposited along the walls of the via hole.
For example, as shown in FIG. 1A, a conventional via structure 100 includes a substrate 110 having an overlaying first conductor layer 112, an insulator layer 114 that includes a via hole 116 overlaying first conductor layer 112, and a second conductor layer 118 overlaying insulator layer 114 and forming by way of via hole 116 in insulator layer 114 a connection with first conductor layer 112.
Substrate 110 is formed of any standard substrate material that is suited for multi-layer electronic devices. Non-limiting examples of such materials include anodized aluminum, flexible steel foil, glass and plastic. First conductor layer 112 and second conductor layer 118 are formed of typical metals used to form interconnections in semiconductor fabrication, such as, without limitation, aluminum, gold, copper, nickel, titanium, a metal alloy or a metal compound. Insulator layer 114 is a non-conductive layer that is formed of any common circuit insulator material, such as, without limitation, aluminum oxide (Al2O3) or tantalum pentoxide (Ta2O5).
With reference to FIG. 1B and with continuing reference to FIG. 1A, a cross-sectional view of via structure 100 shows second conductor layer 118 deposited atop insulator layer 114 such that conductor layer 118 follows the contour of via hole 116 thereby making direct contact with the surface of first conductor layer 112 by way of via hole 116. Via hole 116 has a height hVIA that equals the thickness of insulator layer 114 and second conductor layer 118 has a thickness tCOND. In the via structure 100 shown in FIG. 1B, tCOND equals or exceeds hVIA whereupon second conductor layer 118 follows the contour of insulator layer 114 into and out of via hole 116 and atop first conductor layer 112 without any discontinuity in its structure.
With reference to FIG. 1C and with continuing reference to FIGS. 1A and 1B, a cross-sectional view of via structure 100 includes first conductor layer 112, insulator layer 114, via hole 116 and second conductor layer 118. However, in the via structure 100 shown in FIG. 1C, tCOND is less than hVIA whereupon second conductor layer 118 does not follow the contour of insulator layer 114 into and out of via hole 116 and atop first conductor layer 112 without any discontinuity in its structure. The larger hVIA of via hole 116 compared to a smaller tCOND creates a risk of a discontinuity 120 occurring in second conductor layer 118. It is widely accepted by those skilled in the art that this risk of discontinuity is present anytime that the value of hVIA exceeds the value of tCOND.
A continuous inline vapor deposition shadow mask process also presents a technical challenge in making via holes without disrupting the process. For example, it is inefficient and impractical to insert one or more photolithography steps into the inline vapor deposition shadow mask process.
Therefore, what is needed, and not disclosed in the prior art, is a method and apparatus for use in an automated vapor deposition shadow mask vacuum deposition process that facilitates the formation of continuity between two conductors through a via hole where the value of hVIA exceeds the value of tCOND.